Transistor vertical deflection circuits



May Z6, 1964 L. A. FREEDMAN TRANSISTOR VERTICAL DEFLECTION CIRCUITS Filed March 23, 1962 2 Sheets-Sheet 1 lllirlfwal lh|| May 26, 1954 L. A. FREEDMAN 3,134,928

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LARRY AFREEDMAN United States Patent O 3,134,928 'IRANSISTGR VERTICAL DEFLECTlGN CIRCUITS Larry A. Freedman, East Brunswick, NJ., assigner to Radio Corporation of America, a corporation of Delaware Filed Mar. 23, 1962, Ser. No. 181,909 4 Claims. (Cl. 315-27) This invention relates to television receiver circuits, and more particularly to transistorized circuits for generating vertical deilection signals to apply to the vertical deflection windings of an electromagnetic deflection yoke for a cathode ray image reproducing tube of a television receiver.

In order to reproduce an image on the screen of a cathode ray tube in a television receiver, the electron beam of the tube is caused to scan a raster on the screen of the tube so that light is emitted therefrom in a series of vertically-spaced, horizontal lines. The electron beam is thus deflected both vertically and horizontally from its normal undellected position. One method of providing such deflection is to use an electromagnetic deflection yoke which includes both horizontal and vertical deflection windings through which the proper currents are driven to provide the desired time varying magnetic deilecting field for the electron beam of the cathode ray tube.

Present day commercial television receivers using electron tubes employ a variety of circuits for generating vertical deilection signals to apply to the vertical deilection windings of a yoke. One such circuit uses the multivibrator principle, in which a capacitor is charged through a relatively high impedance from a source of direct voltage. The charging Voltage across the capacitor is applied to an amplifier tube to generate a generally sawtooth shaped current for application to the vertical deilection windings of the yoke. A discharge or switch tube is utilized to short and discharge the charging capacitor at the proper time to retrace the beam back to its starting position and begin the cycle again. The time of initiation of the cycle is synchronized by the vertical deflection synchronizing signals transmitted to the receiver along with the image information. The deilection circuit is made self-oscillating, however, by feeding back to the switch tube a retrace voltage pulse that is developed when the current through the inductive vertical deflection windings is cut oil?.

The techniques of designing and constructing vertical deflection circuits with electron tubes cannot` be directly applied to transistors because the transistors are essentially low impedance, current-operated devices, while the. electron tube is essentially a high impedance, voltageoperated device.

In accordance with the invention, a vertical deflection circuit for supplying deflection current to. the vertical deflection windings of an electromagnetic deflection yoke in a television receiver includes a drive or output transistor and a switch transistor. A charging capacitor is connected with the base electrode of the output transistor and is charged from a source of voltage which includes the base-to-emitter path of the output transistor as part of the impedance of the voltage source. The collector-toemitter path of a switch transistor is connected across, the charging capacitor to discharge it during retrace time; and feedback is provided from the collector and 3,134,928 Patented May 26, 1964 emitter of the output transistor to the base of the switch transistor to maintain self-oscillation in the circuit and to provide immunity against noise signals that may accompany the vertical deflection synchronizing signals which are applied to the base of the switch transistor.

The invention may be better understood when the following detailed description is read in connection with the accompanying drawings in which:

FIGURE l is a schematic circuit diagram, partly in block form, of a television receiver utilizing a vertical deflection circuit in accordance with the invention;

FIGURE 2 is a series of waveforms showing certain operational features of the circuit of FIGURE l; and

FGURES 3 and 4 are schematic circuit diagrams illustrating other embodiments of the invention.

FIGURE l shows a television receiver which includes an antenna 10 to intercept and supply a radio frequency television wave to the tuner and IF amplifier' circuits 12 of the receiver. The radio frequency wave has a picture carrier, amplitude modulated with video signals including image signals and horizontal and vertical detlection synchronizing signals; and a sound carrier, spaced 4.5 megacycles in frequency from the picture carrier according to present broadcasting standards, frequency modulated with sound signals. An amplified intermediate frequency version of the radio frequency wave is available at the output of the tuner and 1F amplifier 12 and is applied to a Video detector 14, where the amplitude modulation of the intermediate frequency wave is detected to provide video signals containing image signals and horizontal and vertical deflection synchronizing signals, and in which the picture and sound I-F carrier waves are heterodyned 'to provide a 4.5 megacycle inter-carrier wave which is frequency modulated with the sound signals. The detected video signals and the intercarrier wave are applied to a video amplifier 16, from which the intercarrier wave is further applied to a sound channel 18 where it is demodulated and further applied to a loudspeaker 2@ to reproduce the sound information.

The image signals are applied from the video amplifier 16 to the electron gun (not shown) of a cathode ray image reproducing tube 22 to modulate the intensity of the electron beam of theV tube in accordance with the image signals. The video signal is further applied to an automatic gain control circuit 24 which generates a control voltage from the video signals to control the gain of prior amplifiers in the receiver, such as the radio frequency and intermediate frequency amplifiers in the tuner and IF amplifier 12, to maintain the amplitude changes in the detected video signals within a small range despite any large changes in the amplitude of the received radio wave.

The video signals are also applied to a synchronizing signal separator circuit 26 which separates the horizontal and vertical deflection synchronizing signals from the remainder of the video signals. T he horizontal synchronizing signals are applied to a horizontal deflection crcuit 2S (which may be of known design) to generate horizontal deflection signals which are available at the terminals H-H and applied to the terminals H-H of the horizontal dellection windings 36 in an electromagnetic deflection yoke (which comprises horizontal dellection windings 30 and vertical dellection windings 54 positioned on the cathode ray tube 22). The currents thus caused in the horizontal deflection windings 30 cause deflection of the electron beam of the tube in a horizontal direction.

Vertical synchronizing signals available from the synchronizing signal separator circuit 26 are applied to a vertical deection circuit, embodying the invention, which includes an output transistor 32, having a base 34, an

emitter 36, and a collector 38; and a switch transistor 40,y

having a base 42, an emitter 44, and a collector 46. The collector 38 of the output transistor 32 is connected to a source of operating voltage, -B, through the primary winding 48 of a vertical output transformer 50. The secondary winding 52 of the transformer 50 is connected to the vertical deiiection windings 54 of the yoke through the terminals V-V. One side of the secondary winding 52 is connected to ground for the receiver, or to some other point of reference potential. The secondary winding 52 is shunted by a bypass capacitor 56 to bypass signals at the horizontal deflection frequency.

In order to supply a sawtooth driving signal, modified in a manner explained hereinafter, to the base 34 of the output transistor 32, a charging capacitor S8 is connected between the base 34 and ground, or a point of reference potential, for the receiver. The base 34 is also connected through a fixed resistor 60 and a Variable resistor 62, which serves as a vertical size control, to the source of operating potential, e-B. The sawtooth wave is formed by the charging of the charging capacitor 58 from the voltage supply, -B. Note, however, that the base-toemitter path of the output transistor 32 shunts the supply voltage and, because this is a relatively low impedance path compared to the resistors 60 and 62, its impedance primarily determines the charging time constant resistance for the sawtooth capacitor 58.

The base-to-emitter impedance of a transistor is relatively low and in order to increase this impedance, an emitter resistor 64 is connected between the emitter 36 of the output transistor 32 and ground for the receiver. The effective input impedance of the output transistor 32 is thus approximately Re, where is the current gain of the transistor and Re is the value of the emitter resistor 64. However, this impedance is still small, since a typical value for the input impedance of the transistor 32 is on the order of 300 ohms, including the etfect of the emitter resistor 64. This value in combination with a reasonable sized capacitor 58 (that is, one that can be discharged without excessive currents being drawn during retrace time) results in a time constant which is on the order of the period of the vertical deiiection frequency, which time constant is much too short to provide the proper shaped driving voltage to the output transistor 32.

The driving voltage is properly shaped, however, by feedback from the secondary 52 of the transformer 50 to the base 34. The secondary winding 52 is poled in the opposite direction to the primary'so that the feedback to the base 34 is degenerative during the first portion of the trace interval (that is, during the rst portion of the charge time of the capacitor 58) and regenerative for the remainder of the trace interval.

This type of feedback, when properly proportioned, provides a current through the vertical windings 54 which is not exactly a linear rising sawtooth, but rather a linear rising sawtooth with an S-shaped component added to it. The resultant current waveform through the vertical windings 54 is shown as curve 106 in FIGURE 2, and is the type of waveform required for linear vertical deflection in wide-angle cathode ray picture tubes. A linearity control potentiometer 66 and limit resistor 68 are included in the feedback connection. VVariation of the value of the linearity control 66 varies theamount of feedback and thus the shape of the driving voltage on the base of the outputV transistor 32. e

In order to maintain self-oscillations in the circuit, the voltage appearing at the collector 38 of the output transisto-r 32 is fed back through a high pass lter network 70 and a storage capacitor 72 to the base electrode 42 of the switch transistor 40. A frequency or hold control is provided by connecting a limit resistor 74 and a hold potentiometer 76 in series between the sourec of operating potential, -B, and ground. A voltage divider comprising a pair of resistors 78 and 80 is serially connected between an adjustable tap 82 on the hold potentiometer 76 and ground for the receiver. The base 42k of the switch transistor 40 is connected to the junction of the voltage divider resistors 78 and 80. The collector 46 of the switch transistor 40 is connected directly to the base 34 of the output transistor 32 and the emitter 44 of the switch transistor 40 is connected directly to ground. Thus, the collector-to-emitter path of the switch transistor 40 is connected directly across the charging capacitor 58. A signal appearing across the emitter resistor 64 of the output transitor 32 is also connected through an isolating resistor 84 to the base electrode 42 of the switch transistor The operation of the circuit is best described by assuming that the charging capacitor 58 is initially discharged. The charging capacitor 58 begins to charge in a negative direction toward the value of the operating voltage, -B, as shown at 'to in curve 100 of FIGURE 2. All of the waveformsin FIGURE 2 are drawn on the same time scale to illustrate the voltages and currents appearing'at various pointsrin the circuit.V From t0 to t1 is the trace interval and from t1 to t2 is the retrace interval. As the voltage begins to increase in a negative direction: across the charging capacitor 58, the output'transistor 32 begins to conduct when the voltage across the charging capacitor 58 becomes negative, and the voltage at the emitter 36 of the output transistor 32 also begins to increase in a negative direction as shown by curve 102. The voltage at the collector 38 begins at to to-rise towards zero as shown in curve 104, and the current through the yoke winding 54 begins to decrease from its maximum current in one direction at to to its maximum current inthe opposite direction at t1, as shown in curve 106. At to the trace interval is beginning, and light is emitted from the screen of the cathode ray tube 22. The voltage at the base 42,Y of the switch transistor 40 is positive as shown in curve 108 and is beginning to drop towardsrzero.

As the end of the trace interval is reached at t1 the voltage on the base 42 ,of the switch transistor reaches the point where the switch transistor 42 can conduct, and conduction of the switch transistor 40 abruptly discharges the charging capacitor 58, as shown in curve 100. This action abruptly reduces the current through the vertical deflection winding 54 and generates a large retrace voltage pulse thereacross. The retrace voltage pulse is coupled back through the transformer 50 and appears on the collector electrode 38 of the output transistor 32 as shown in curve 104. The retrace voltage pulse is applied back e through the highpass filter to the base electrode 42 of the switch transistor 40, causing heavy base current which charges the storage capacitor 72 highly positive to maintain the switch transistor 40 cut off after the cessation of the retrace pulse. Y

With the turn-ing o of the switch transistor 40 the charging capacitor .58 lagain begins to charge to *repeatV the cycle. The 'frequency of operationof the circuit as a free rimning'oscillator is determined by the time it takes the storage capacitor 72 to discharge again to aY point where the switch transistor y40 can again conduct. Note that the storage capacitor 72 discharges through the resistors 80, 78 and the hold control potentiometer 76. Variation of the tap 82 on the hold control potentiometer 76 thus varies the discharge time of the storage capacitor 72 and varies the frequencyY of operation of the circuit. 'The shape of thevoltlage on the base 42 between t0 and t1 is derived from the combination of the discharge of the storage capacitor 72, lan S-shaped wave derived throu-gh Y the high pass filter 70 from the collector 38 of the output transistor 32, and from the nearly sawtooth wave (curve 102, FIGURE 2) on lthe emitter electrode 36 of the output transistor 32. The high pass tilter 70 eliminates the sawtooth portion of the collector voltage shown during the trace time in curve 104 and passes only the high lfrequency S-shaped portion. The combination of these two voltages provides a voltage having the waveform shown `as curve 108 which -aids in holding the base 42 of the switch transistor 40 quite positive until near the end of trace interval.

Vertical synchronizing sign-als from the synchronizing signal separator circuit. 26 `are applied through the isolatling resistor 86 and the storage capacitor '72 to the base electrode 42 of the switch transistor 40. A negative going vertical signal is used and it abruptly drives the base 42. negative to `cause the switch transistor 40 to conduct and initiate the discharge of the charging capacitor 58. This act-ion synchronizes the operation of the circuit with the vertical synchronizing signals contained in the received television signal.

Note that the voltage on Ithe base 42 of the switch transistor 40 as-shown in curve 10S, FIGURE 2 is maintained highly positive during the trace interval, maintaining the transistor l4t) well -below cutot for the major portion of the trace time. This provides a high degree of noise immunity for the circuit, because low amplitude noise signals, which might ap-pear with the vertical synchronizing signals, yare unable to turn the switch transistor 40 `on and cause incorrect operation.

The typical values for a vertical deection circuit constructed in accordance with the invention for use with a cathode ray tube having a 1110" deection angle and operating with 18,000 volts vand using a yoke having vertical deection windings with 6 ohms resistance and 18 millihenries inductance `are as follows:

Resistor 60 ohms-- 2700 Resistor 62 ohms variable 2500 Resistor 66 do 250 Resistor 68 do 270 Resistor 64 ohms 4.7 Resistor 74 do 33,000 Potentiometer 76 do- 50,000 Resistor 78 do 33,000 Resistor -80 do 6800 Charging capacitor S microfarads-.. 50 Storage capacitor 72 -..do 1

The values of resistors and capacitors in the iilter network are shown in the drawing. The output transistor 32 is a .commercially `available RCA type 2N301A and the switch transistor 40 is a commercially available RCA type 2N404. The circuit provided a yoke current in the vertical deflection windings 54 `of 1.2 vani-peres peak-to-peak to provide full deflection of the beam of the cathode ray tube. The frequency shift of the circuit, as a free running oscillator, for an opera-ting voltage change of 24 to 34 volts was less than i0.5 cycle per second. A frequency increase of between 1.7 Iand 3 cycles per second was noted when the temperature of 'the entire circuit w-as raised from 25 C, to 62 C.

FIGURE 3 shows `a partial schematic diagram of the output stage connected with the output transistor 32 to illustrate that capacitive coupling may be used between the circuit Iand the vertical deilecti-on windings 54 instead of transformer coupling. A choke coil 48 is connected between the collector 38 of the output transistor 32 and the source of operating voltage, l-B. A coupling capaci- Itor 90 is connected between the collector 3.8 and one side of the` vertical deflection windings 54 and the other side of the windings is connected directly to the source of operating voltage, K-B. In order to provide the feedback 'to the base 34, yan auxiliary winding 52' is magnetically coupled to the .choke coil 4S and bypassed at horizontal frequencies by a bypass capacitor 56. One end of the auxiliary ywinding 52 is connected directly to ground and the other end is connected through the linearity control 66 `and the limit resistor 68 to the base 34 of the output transistor 32. The remainder of the circuit is identical `to that shown in FIGURE f1 and operates in the same manner, with the exception that the current from the collector 38 of the output transistor 3-2 `for driving the Vertical windings is coupled through the capacitor instead of `a transformer as shown in .FIGURE 1.

Direct coupling of the vertical deflection windings 54 to the output transistor 32 may be used as shown in the partial schematic diagram of FIGURE 4 which is identical to the circuit diagram of FIGURE 3 with the exception .that the coupling capacitor 90 shown in FIGURE 3 has been eliminated. The operation of the FIGURE 4 circuit is identical to that shown in FIGURE 3. yIt will be appreciated, however, that a certain amount of direct current will flow through the vertical windings 54 resul-ting in .a slight decentering of the raster on the screen of the cathode ray tube 22. This decentering may be corrected, as is known, by the use of permanent magnet center-ing devices.

What is claimed is:

1. In a television receiver having a cathode ray image reproducing tube, vertical deilection windings for said tube, and a source of vertical synchronizing signals, a vertical deection circuit comprising in combination:

a first transistor having a base, a collector, and an emitter;

a charging capacitor connected to the base of said first transistor;

a charging circuit for said capacitor including a source of direct voltage connected to said capacitor;

a discharge circuit for said capacitor including a second transistor having a base, a collector, and an emitter, and having the collector-toemitter path of said second transistor connected across said capacitor;

rst feedback means connected between the collector of said rst transistor and the base of said second transistor for providing self-oscillations in said circuit sequentially to charge said capacitor during a charging cycle through said charging circuit, and to discharge said capacitor during a discharge cycle through the collector-to-emitter path of said second transistor;

coupling means for connecting the vertical deflection windings to the collector of said rst transistor for supplying deilection current thereto;

second feedback means coupled between said collector of said Iirst transistor and the base of said tirst transistor such that the feedback signal applied to said rst transistor is degenerative during the first part of the charging cycle of said charging capacitor and regenerative during the second part of the charging cycle of said charging capacitor;

third feedback means connected between the emitter of said first transistor and the base of said second transistor for applying during said charge cycle a voltage to the base of said second transistor which near the end of said charge cycle is abruptly changing in a direction tending to turn on said second transistor; and

means for applying said vertical synchronizing signals to said second transistor to initiate the discharge cycle of said capacitor and synchronize the frequency of said self-oscillations to said vertical synchronizing signals.

2. In a television receiver having a cathode ray image reproducing tube, vertical deiection windings for said tube, and a source of vertical synchronizing signals, a vertical deflection circuit comprising in combination:

a first transistor having a base, a collector, and an emitter;

a charging capacitor connected to the base of said iirst transistor;

a charging circuit for said capacitor including a source of direct voltage connected to said capacitor;

a discharge circuit for said capacitor including'a secsecond transistor, said first feedback means applying ond transistor having a base, a collector, and an emitter, and having the collector-to-emitter path of 4said second transistor connected across said capacitor;

sistor for applying a feedback signal to said first transistor that is degenerative during the first part of the charging cycle of said charging capacitor and regenerative during the second part of the charging during the discharge cycle a retrace pulse, generated across said vertical deflection winding, to the base of said second transistor to rapidly discharge said first feedback means including a storage capacitor cron-v 5V charging capacitor and to charge said storage capacinected between the collector of said first transistor tor in a polarity to cutoff said second transistor;

and the base of said second transistor for providing second feedback means connected between the emitter self-oscillations in said circuit sequentially to charge of said first transistor and the base of said second said charging capacitor during a charging cycle transistor for applying during said charge cycle a Y through said charging circuit, and to discharge said voltage to the base of said second transistor which charging capacitor during a discharge cycle through near the end of said charge cycle is abruptly chang'- the collector-to-emitter path of said second transising in a direction tending to turn on said second tor and torcharge said storage capacitor in a polarity transistor; Y to maintain said second transistor non-conductive third feedback means coupled between said collector during the succeeding charge cycle; Y of said first transistor and the baseiof said first trancoupling means for connecting the vertical deection Vsistor Snell that the feedback Signal applied to said i windings to the collector of said first transistor for first transistor is degenerative during the first part of supplying deflection current thereto; the charging cycle of said charging capacitor and second feedback means coupled between Vsaid collector regenerative during the second part of the charging of said first transistor and the base of said first tran- Cycle 0f Said charging capacitor; and

coupling Vmeans for connecting the vertical deflection windings between the collector and emitter of said second transistor for supplying said dellection current thereto.

4.7111 a television receiver Vhaving a cathode ray image reproducing tube, vertical deflection windings for said tube, and a source of vertical synchronizing signals Va vertical deflection circuit comprising in combination:

a first transistor having a base, a collector, and an cycle of said charging capacitor such that the rate of change of deflection current is Vless than that of a linear sawtooth current near the beginning and near the end of the charge cycle and greater than that of a linear sawtooth current during the remaining intermediate portion of the charge cycle; emitter; third feedback means connected between the emitter a Charging Capacitor Conneeted t0 the base Of Said first of said first transistor and the base of said second transistor;

a charging circuit for said capacitor including a source of direct voltage connected to said capacitor;

a discharge circuit forv said Ycapacitor including a second transistor having aV base, a collector, and an emitter, and having the collector-to-emitt'er path of said second transistor connected across said capacitor;

first feedback'mea'ns including a high pass filter network and a storage capacitor connected between theV collector of said first transistor and the base of said second transistor for providing Vself-oscillationsnin saidcircuit sequentially to charge` saidapa'citior(diuring' aV charging cycle through said charging circuit and generate a deflection current in kthe collector-totransistor for applying during said charge cycle a voltage to the base of said second transistor which near the end of saidV charge cycle is abruptly changing in a direction tending to turn on said second transistor; and means for applying said vertical synchronizing signals to said second transistor to initiate the discharge cycle of said capacitor and synchronize the frequency of said self-oscillations to said vertical synchronizing signals. 3. In a television receiver having a cathode ray image reproducing tube and vertical deflection windings for said tube, a vertical deflection circuit comprising in combiis changing in a direction tending to turn on said nation: Y Y emitter path of's'aidirst tra'nsisto`r,randY to discharge a first transistor having a base, a collector, and an said* Charging Capaoitor during a flisollargeioyole emitter; through the collector-to-emitter path of said second a charging capacitor connected to the base of said first transistor; t

transistor; Y 50 said first feedback means applying, during the charge a charging circuit for said capacitor including a source cyclel the high frequency component 0f the voltage of direct voltage connected to said capacitor; appearing 0n the Colleotor 0f said iirst transistor t0 a discharge circuit for said capacitor including a second the base of said Second transistor Which tends to transistor having a base, a collector, and an emitter, maintain the second transistor cutoti during the and having the collector-to-emitter path of said sec- Charge Cycle, but Wllich at the end of the Charge ond transistor connected Vacross said capacitor; 'Cycle is Changing in a direction tending 4tortllrll 011Vv rst feedback means including a high pass filter netseid second transistor, said first feedback means apwork and a storage capacitor connected between the plying during the discharge Ycycle a retrace puise, collector of said first transistor and the base of said generated aCrOsS-Said vertical Winding, to the base of second transistor for providing self-oscillations in Said SeCOnd transistor to rapidly discharge said chargs'aid circuit sequentially tc charge said capacitor during capacitor and te charge said storage Vcapacitor in Y ing a charging cycle through said charging circuit Y a Polarity t0 .Cutoff Said Second tranSiStOr; i I and generate a deflection current in the, collecter-,t0- second feedback means connected between the emitter emitter path of said first transistor, and to discharge of said first transistor and the base of said second( said charging capacitor Vduring a discharge cycle transistor for applying during :saidrcharge cycle a through the collector-to-emitter path of said second Voltage to the base of' Said-Second transistor which transistor; i i g near the end of said charge cycle is abruptly changsaid first feedback means applying, during the charge ving in a direction tending to turn on said second cycle, the high frequency component of the voltage 7 transistor; Y Y appearing on the collector of said first transistor to third feedback means coupled between said collector the base of said second transistor which tends to of said first transistor and the base of said first tranmaintain the second transistor cutofic during the sistor such that the feedback signal applied to said charge cycle, but which at the end of thercharge cycle first transistor is degenerative during the first part of the charging cycle of said charging capacitor'and regenerative during the second part of the charging cycle of said charging capacitor;

coupling means for connecting the vertical deiiection windings between the collector and emitter of said second transistor for supplying said detlecton current thereto; and

means for applying the vertical synchronizing signals to the base of said second transistor to synchronize the frequency of said self-oscillations to the frequency of said Vertical synchronizing signals.

References Cited in the le of this patent UNITED STATES PATENTS 

1. IN A TELEVISION RECEIVER HAVING A CATHODE RAY IMAGE REPRODUCING TUBE, VERTICAL DEFLECTION WINDINGS FOR SAID TUBE, AND A SOURCE OF VERTICAL SYNCHRONIZING SIGNALS, A VERTICAL DEFLECTION CIRCUIT COMPRISING IN COMBINATION: A FIRST TRANSISTOR HAVING A BASE, A COLLECTOR, AND AN EMITTER; A CHARGING CAPACITOR CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR; A CHARGING CIRCUIT FOR SAID CAPACITOR INCLUDING A SOURCE OF DIRECT VOLTAGE CONNECTED TO SAID CAPACITOR; A DISCHARGE CIRCUIT FOR SAID CAPACITOR INCLUDING A SECOND TRANSISTOR HAVING A BASE, A COLLECTOR, AND AN EMITTER, AND HAVING THE COLLECTOR-TO-EMITTER PATH OF SAID SECOND TRANSISTOR CONNECTED ACROSS SAID CAPACITOR; FIRST FEEDBACK MEANS CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR FOR PROVIDING SELF-OSCILLATIONS IN SAID CIRCUIT SEQUENTIALLY TO CHARGE SAID CAPACITOR DURING A CHARGING CYCLE THROUGH SAID CHARGING CIRCUIT, AND TO DISCHARGE SAID CAPACITOR DURING A DISCHARGE CYCLE THROUGH THE COLLECTOR-TO-EMITTER PATH OF SAID SECOND TRANSISTOR; COUPLING MEANS FOR CONNECTING THE VERTICAL DEFLECTION WINDINGS TO THE COLLECTOR OF SAID FIRST TRANSISTOR FOR SUPPLYING DEFLECTION CURRENT THERETO; SECOND FEEDBACK MEANS COUPLED BETWEEN SAID COLLECTOR OF SAID FIRST TRANSISTOR AND THE BASE OF SAID FIRST TRANSISTOR SUCH THAT THE FEEDBACK SIGNAL APPLIED TO SAID FIRST TRANSISTOR IS DEGENERATIVE DURING THE FIRST PART OF THE CHARGING CYCLE OF SAID CHARGING CAPACITOR AND REGENERATIVE DURING THE SECOND PART OF THE CHARGING CYCLE OF SAID CHARGING CAPACITOR; THIRD FEEDBACK MEANS CONNECTED BETWEEN THE EMITTER OF SAID FIRST TRANSISTOR AND THE BASE OF SAID SECOND TRANSISTOR FOR APPLYING DURING SAID CHARGE CYCLE A VOLTAGE TO THE BASE OF SAID SECOND TRANSISTOR WHICH NEAR THE END OF SAID CHARGE CYCLE IS ABRUPTLY CHANGING IN A DIRECTION TENDING TO TURN ON SAID SECOND TRANSISTOR; AND MEANS FOR APPLYING SAID VERTICAL SYNCHRONIZING SIGNALS TO SAID SECOND TRANSISTOR TO INITIATE THE DISCHARGE CYCLE OF SAID CAPACITOR AND SYNCHRONIZE THE FREQUENCY OF SAID SELF-OSCILLATIONS TO SAID VERTICAL SYNCHRONIZING SIGNALS. 